FPGA Based Block Adaptive Quantization Design and Implementation

Document Type : Original Article

Authors
Abbas Dastmozd 1
Mohammad Reza Mousavi 1
Kourosh Hassanli 1
Sahar Abdi 2
Mahdi Hatam 2
1 Electrical Engineering Department, Shiraz University of Technology, Shiraz, Iran
2 Institute of Mechanics, Shiraz, Iran
10.22034/jssta.2025.493057.1220
Abstract
This paper investigates the implementation of the Block Adaptive Quantization (BAQ) algorithm on FPGA hardware, specifically the Xilinx Virtex-7 FPGA, which is an ideal platform for real-time applications due to its flexibility and parallel processing capabilities. In this study, the BAQ algorithm was optimized using the principles of non-uniform Lloyd-Max quantization. The hardware design consists of adaptive blocks enhanced by techniques such as parallelization and pipelining. The implementation results demonstrate significant reductions in FPGA resource utilization while maintaining high performance and low latency. Evaluations indicate that the proposed method achieves less than 2% difference compared to the reference approach in metrics such as MSE, PSNR, SSIM, and CC, highlighting the algorithm's high accuracy and consistency. Furthermore, the implementation is resource-efficient, utilizing only 10% of DSP48 resources and 30% of LUTs on the Virtex-7 FPGA. This approach provides an effective solution for applications such as data compression in imaging systems and signal processing.
Keywords
Block Adaptive Quantization
Data Compression
FPGA
Subjects
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Space Science, Technology and Applications
Volume 5, Issue 2
March 2026
Pages 89-102

  • Receive Date 09 December 2024
  • Revise Date 29 January 2025
  • Accept Date 11 May 2025